1. Field of the Invention
The present invention relates to a semiconductor integrated circuit capable of testing a memory, in particular testing a memory having a redundant cell and testing a peripheral logic of the memory, using a Built In Self Test (BIST), and a test method thereof.
2. Description of the Prior Art
Recently, the number and the scale of the memories (bit width and the number of words), which have been mounted in a semiconductor integrated circuit (LSI), have been increased. According to this, the number of external pins and the test time which are needed for inspecting the memory mounted in the LSI using a circuit tester from the outside increase.
In contrast to this, importance of a BIST (Built In Self Test, hereinafter referred to as BIST) technology for executing the test of the memory within the LSI has been increased. By using the BIST technology, while being able to inspect the memory using fewer external pins, it becomes possible to simultaneously inspect a plurality of memories within the LSI because of fewer pins being used.
Moreover, there is a case of using a redundant repair method wherein a redundant circuit (word line for repair, bit line for repair, including cell for repair) has been provided beforehand, and a bit line or a word line, in which a memory cell which becomes faulty due to a defect exists, is replaced with the word line for repair or the bit line for repair, so that the faulty cell is repaired. Thereby, the yield of the memory can be improved.
FIG. 12 shows an example of a repair for the memory and a test circuit of a peripheral logic of the memory using a former BIST.
A test pattern generating section 1201 generates a test pattern for a memory 1204, and a comparing section 1202 compares whether output data of the memory 1204 matches with an expected value, judges whether the output data matches with the expected value, and outputs the result to a FAIL terminal.
Information on an address and a bit location of a faulty cell detected by the comparing section 1202 is retained in a repair process section 1203. The information on the stored faulty cell is used to identify a repair word line and a repair bit line which should be repaired.
Moreover, a signal which has branched from an input to the memory 1204 is retrieved into a flip-flop 1205 for observation, and an output of the memory 1204 is controlled using a flip-flop 1206 for control via a selector 1207, so that a scan test for a BIST circuit itself and a peripheral logic of the memory 1204 is carried out.
Thus, in a circuit in which repair processes for the memory using the former BIST are performed, in order to calculate an address which should be repaired, the repair process section has a memory element therein for storing information on a faulty address and a faulty bit, which have been detected as Fail during the test using the BIST, and in order to perform a scan test for the BIST circuit itself and a memory periphery, a flip-flop for observing an input signal into the memory is provided.
As described above, in order to achieve the repair processes for the memory using the BIST, the memory element for storing the information on the faulty address of the memory is required, and in addition, in order to perform the scan test for the BIST circuit itself and the peripheral logic of the memory, the flip-flop for observation for observing the input signal into the memory and the flip-flop for control for controlling an output of memory are required.
Therefore, in order to achieve the repair processes for the memory and the scan test for the BIST, the memory element for repair process and the flip-flop for scan test are needed, so that there has been a problem that the circuit area has been increased.